Four-quadrant multiplier

ABSTRACT

Circuit employing complementary field-effect transistors operated in the triode mode. A signal representing the multiplicand is applied to the gate electrode of one transistor and a signal representing the multiplier is applied to the drain electrode of the same transistor. The complement of the multiplier signal is applied to the drain electrode of the other transistor. A current indicative of the product is available at the common connection of the source electrodes.

The present invention relates to four-quadrant multipliers employing field-effect transistors and particularly to such multipliers which employ complementary type metal oxide semiconductor (MOS) transistors.

In the drawing:

FIG. 1 is a block and schematic circuit diagram of an embodiment of the invention;

FIG. 2 is a schematic circuit diagram of the multiplier of FIG. 1; and

FIG. 3 is a schematic circuit diagram of a second embodiment of the invention.

Referring to FIG. 1, input signal V₁ indicative of a multiplier is applied from input terminal 10 through coupling capacitor 12 to an inverting amplifier 14. Input node 16 of amplifier 14 supplies a composite signal having ac and dc components to the drain electrode 18 of P-type MOS transistor P₁. A complementary signal is applied by amplifier 14 to the drain electrode 20 of N-type transistor N₁. A dc bias V_(B), and a signal v₂ indicative of a multiplicand, are applied to the gate electrode 22 of transistor P₁. The signal source for v₂ is represented by a circle 24. Transistor N₁ receives a dc bias V_(A) at its gate electrode 26. The respective bias levels are such that both transistors operate in the triode mode.

The source electrodes 28 and 30 of the respective transistors are connected to common node 31 at which the source currents I_(S).sbsb.N and I_(S).sbsb.P are summed. Noted that these source currents flow in different directions relative to the node 31. Node 31 connects to a second inverting amplifier 34 with a feedback resistor 32 for maintaining the input node 31 at virtual ground.

The operation of the circuit of FIG. 1 is succinctly described by the equations which follow.

It is known that the drain current I_(D).sbsb.P for a transistor such as P₁ operated in the triode region is:

    I.sub.D.sbsb.P =-K.sub.P [(V.sub.GS.sbsb.P +v.sub.GS.sbsb.P -V.sub.TH.sbsb.P)(V.sub.DS.sbsb.P +v.sub.DS.sbsb.P )-1/2(V.sub.DS.sbsb.P +v.sub.DS.sbsb.P).sup.2 ]                                 (1)

where, in all cases, the subscript P refers to the P type transistor P₁ and where:

K_(p) = a process related and geometric conductance factor

V_(gs).sbsb.p = the dc component of the gate-to-source voltage

V_(GS).sbsb.P = the ac component of the gate-to-source voltage

V_(th).sbsb.p = the threshold voltage

V_(ds).sbsb.p = the dc component of the drain-to-source voltage

V_(DS).sbsb.P = the ac component of the drain-to-source voltage.

Let V_(GS).sbsb.P -V_(TH).sbsb.P =V_(x) and assume V_(DS).sbsb.P =0 (it will be shown later that this assumption is valid)

    I.sub.D.sbsb.P =-K.sub.P [(V.sub.x +v.sub.GS.sbsb.P)v.sub.DS.sbsb.P -1/2v.sub.DS.sbsb.P.sup.2 ]

so that: ##EQU1##

The drain current I_(D).sbsb.N for transistor N₁ is (keeping in mind that a signal is not being applied to its gate electrode 26 and assuming that V_(DS).sbsb.N, the source-to-drain dc component is zero):

    I.sub.D.sbsb.N =+K.sub.N [V.sub.y v.sub.DS.sbsb.N -1/2v.sub.DS.sbsb.N.sup.2 ]                                                         (3)

where:

V_(y) -V_(GS).sbsb.N -V_(TH).sbsb.N

k_(n) = a process related and geometric conductance factor for transistor N₁

V_(gs).sbsb.n = the dc component of the gate-to-source voltage of transistor N₁

V_(th).sbsb.n = threshold voltage of transistor N₁

v_(DS).sbsb.N = the ac component of the drain-to-source voltage of transistor N₁

    |v.sub.gs.sbsb.n |>|v.sub.th.sbsb.n |

by inspection:

    I.sub.SUM =I.sub.S.sbsb.P +I.sub.S.sbsb.N                  (4)

    i.sub.s.sbsb.p =i.sub.d.sbsb.p                             (5)

    i.sub.s.sbsb.n =i.sub.d.sbsb.n                             (6)

where:

I_(s).sbsb.p = source current of P₁

I_(s).sbsb.n = source current of N₁

Substituting equations (2), (3), (5) and (6) into equation (4) gives:

    I.sub.SUM =-K.sub.P V.sub.x v.sub.DS.sbsb.P -K.sub.P v.sub.GS.sbsb.P v.sub.OS.sbsb.P +K.sub.N V.sub.y v.sub.DS.sbsb.N -1/2K.sub.N v.sub.DS.sbsb.N.sup.2 +1/2K.sub.P v.sub.DS.sbsb.P.sup.2   (7)

which simplifies to: ##EQU2##

In the ideal case,

K_(P) =K_(N)

v_(x) =-V_(y)

V_(DS).sbsb.P =v_(DS).sbsb.N

so that the α and β terms cancel leaving the desired product term K_(P) v_(GS).sbsb.P v_(DS).sbsb.P.

For the non-ideal case, gain adjustment of amplifier A₁ can be employed to zero the β term, and adjustment of the dc component at the gate electrode of the P or N type transistor can be employed to zero the α term.

While in the embodiment of FIG. 1, the multiplicand is applied only to the gate electrode 22 of a P-type transistor P₁, in a modified form of the circuit a signal complementary thereto, that is v₂, can be applied to the gate electrode 26 of N-type transistor N₁.

In equation 8 above, the product term K_(p) v_(GS).sbsb.P v_(DS).sbsb.P is a current proportional to the product v₁ v₂, with K_(p) a constant. The function of the output amplifier 34 is to translate this current to a voltage Kv₁ v₂, where K is a constant.

The circuit of FIG. 2 is a complementary symmetry metal oxide semiconductor (COS/MOS) realization of the circuit of FIG. 1. All transistors are of the enhancement type. Inverter pair P₂, N₂, with each transistor connected gate electrode-to-drain electrode, serves as a biasing means for holding the common gate connection 40 of the following transistor pair P₃, N₃ at a desired dc voltage level. In a preferred form of the invention, transistors N₂ and P₂ are matched as are transistors P₃ and N₃, and P₄ and N₄, that is, all of these transistors are fabricated to have the same conduction path impedance in response to corresponding operating voltages. As transistors P₂ and N₂ are matched, the common gate electrode connection 40 is at a dc level V_(C) /2. The COS/MOS inverter P₃, N₃ is interconnected with the diode-connected transistor P₂, N₂ to form a COS/MOS current mirror amplifier. The quiescent or dc output voltage at the interconnected drain electrodes (connection 42) of this amplifier is V_(C) /2. These drain electrodes connect to the gate electrode of transistor P₄, which operates as an inverter. Transistor N₄, which is connected at its source electrode to ground and at its common drain-gate electrode connection to the drain electrode of transistor P₄, serves as a resistive load for transistor P₄.

The multiplier signal v₁ is applied through capacitor 12 to common connection 42 at the drain electrode of the multiplying transistor P₁. Note that the voltage at 42 includes a dc component V_(C) /2 and an ac component v₁. An ac signal complementary to v₁ appears at the drain electrode to transistor P₄ and is applied to the drain electrode of transistor N₁. Note that here also there is a dc component V_(C) /2 as well as the ac component.

The output inverting amplifier A₂ comprises a further COS/MOS matched pair P₅, N₅. The feedback resistor 32 is connected between the common drain electrode connection 33 and the common gate electrode connection 31. Connected in this way, the amplifier P₅, N₅ is biased to the same dc level as are the amplifiers P₃, N₃ and P₄, N₄, assuming V_(D) =V_(c). Under these conditions, the drain electrodes of transistors N₁ and P₁ are at the same dc potential as their source electrodes so that the assumption made (V_(DS).sbsb.P =0) in deriving equation 2 is valid and holds also for N-type transistor N₁. If the transistors are not perfectly matched, the dc component just discussed can be eliminated by differential adjustment of the operating voltages V_(C) and V_(D), assuming, as is the case in practice, that the impedance looking into the source electrodes of the transistor pair N₁, P₁ is high compared to the dc impedance looking into the amplifier P₅, N₅. In practice, of course, V_(C) and V_(D) can be a common voltage source provided with some differential means of adjustment such as a variable resistor in one or both power supplies leads.

In the embodiment of the invention illustrated in FIG. 3, a differential amplifier is employed for obtaining the complementary signals. The amplifier comprises two MOS pairs P_(A), N_(A) and P_(B), N_(B). Both pairs receive supply current from a common current source 50. The gate electrode of the transistor P_(B) of the second pair is maintained at a dc reference voltage level. The reference voltage source is indicated schematically by a battery 52 but it may be obtained by a circuit which includes a Zener diode or by a circuit comprising a string of series connected diodes between two operating voltage terminals with a tap being taken from a suitable place along the diode string. The same holds for source 54 which provides the dc bias for the gate electrode of transistor P_(A) of the first pair. The latter gate electrode also receives the ac multiplier signal v₁ from source 56.

The operation of the circuit of FIG. 3 is believed to be self-evident from the description which already has been given. When an ac signal v₁ is present, the current from source 50 will divide among the two branches of the differential amplifier in accordance with the amplitude and polarity of the signal. For example, as v₁ goes more positive, current flow through transistor P_(A) decreases and the ac signal component at node 58, which is supplied to the drain of transistor N₁, becomes less positive. Correspondingly, the ac signal component appearing on lead 60, which is applied to the drain electrode of transistor P₁ becomes more positive. In other words, the signals on leads 58 and 60 are complementary to one another, the one on lead 60 being of the same polarity as the input signal and the one on lead 58 being complementary thereto. This is similar to what occurs in the circuit of FIGS. 1 and 2. The remainder of the circuit operation is the same as discussed in connection with FIGS. 1 and 2.

It is known in the art to employ field-effect transistors of the same conductivity type (as contrasted to the complementary conductivity type transistors P₁, N₁ used here) to provide a four-quadrant multiplication. Patents showing representative multipliers employing such structure are U.S. Pat. No. 3,562,553 to Roth and U.S. Pat. No. 3,368,066 to Miller et al. However, these prior circuits require a differential amplifier, such as shown at 80 in Roth, for combining the outputs of the multiplying transistors with one another to obtain the product signal, whereas in the present application the addition takes place at a common connection 31. A differential amplifier limits the bandwidth of the circuit. For example, it is expected that the circuits of the present FIG. 3 can be operated in the 20 MHz range and the same would hold for the prior art circuit which require a differential amplifier to combine currents. On the other hand, the circuit of FIG. 2 is expected to operate in the 60 MHz range. Further, the use of a differential amplifier introduces possible problems of common mode rejection.

Another feature of the present circuit is that it is easily compatible with a system which employs complementary transistors in other portions of the system. This is especially useful where integration of all circuits on a common semiconductor substrate is desired as the manufacturing steps are the same for the multiplying transistors N₁ and P₁ as for the remaining transistors. 

What is claimed is:
 1. A multiplier for developing a product signal proportional to a multiplicand signal multiplied by multiplier signal comprising, in combination:first and second field effect transistors respectively of first and second conductivity types complementary to each other, each having source and drain electrodes and a channel therebetween and having a gate electrode; means for maintaining the source electrodes of said first and second transistors at a reference potential; means for applying to the drain electrode of said first transistor a first drain potential having a direct component equal to said reference potential and having a component indicative of said multiplier signal superimposed on its direct component; means for applying to the gate electrode of said first transistor a first gate potential having a direct component for operating said first transistor in its triode region and having a component indicative of said multiplicand signal superimposed on its direct component; means for applying to the drain electrode of said second transistor a second drain potential having a direct component equal to said reference potential and having a component indicative of said multiplier signal superimposed on its direct component, the components of said first and second drain potentials indicative of said multiplier signal being complementary or anti-phase to each other; means for applying to the gate electrode of said second transistor a second gate potential for operating said second transistor in its triode region; and means connected to additively combine the currents flowing in the channels of said first and second field effect transistors responsive to the potentials applied to them to derive said product signal substantially free of first-order and second-order multiplier signal terms.
 2. A multiplier as set forth in claim 1 wherein at least one of said means for applying a first gate potential and said means for applying a second gate potential includes means for adjusting the direct component of the gate potential it applies to null first-order multiplier signal terms from said product signal.
 3. A multiplier as set forth in claim 1 wherein at least one of said means for applying a first drain potential and said means for applying a second drain potential includes an adjustable gain amplifier for adjusting the relative amplitudes of the components of said first and second drain potentials indicative of said multiplier signal to null second-order multiplier signal terms in said product signal.
 4. A multiplier as set forth in claim 3 wherein at least one of said means for applying a first gate potential and said means for applying a second gate potential includes means for adjusting the direct component for adjusting the gate potential it applies to null first-order multiplier signal terms from said product signal.
 5. A multiplier as set forth in claim 1 wherein said means connected to additively combine the currents flowing in the channels of said first and second transistors is an output amplifier, having an input terminal maintained at said reference potential, to which input terminal the source electrodes of said first and said second transistors connect, and having an output terminal at which said product signal is available.
 6. A multiplier as set forth in claim 5 including:third and fourth field effect transistors of said first and second conductivity types, respectively, each having source and drain and gate electrodes; means connecting said third and fourth transistors as said output amplifier, including a connection of the gate electrodes of said third and fourth transistors to the input terminal of said amplifier, a connection of the drain electrodes of said third and said fourth transistors to the output terminal of said amplifier, a feedback resistor connected between the output and input terminals of said output amplifier, and means for applying a first operating potential between the source electrodes of said third and fourth transistors; fifth and sixth field effect transistors of said first and said second conductivity types, respectively, each having source and drain and gate electrodes; means connecting said fifth and said sixth field effect transistors as a signal-inverting amplifier, including an input terminal connected to the gate electrode of said fifth transistor for receiving a potential with a dc component upon which said multiplier signal is superimposed, an output terminal having the drain electrodes of said fifth and sixth field effect transistors and the gate electrode of said sixth transistor connected thereto, and means for applying a second operating potential between the source electrodes of said fifth and sixth transistors, said first and second operating potentials being adjustable with respect to each other for nulling multiplier signal terms in said product signal; and connections of the input and output terminals of said signal inverting amplifier to separate ones of the drain electrodes of said first and second transistors, thereby providing the means for applying said first drain potential and the means for applying said second drain potential.
 7. A multiplier as set forth in claim 6 wherein the multiplier signal is coupled via a capacitor to the input terminal of said signal inverting amplifier and wherein a direct component of potential is applied to the input terminal of said signal inverting amplifier by means comprising:seventh and eighth field effect transistors of a first conductivity type and ninth and tenth field effect transistors of a second conductivity type, each having source and drain and gate electrodes; connection of the source electrodes of said seventh and eighth transistors to the source electrode of said fifth transistor; connection of the source electrodes of said ninth and tenth transistors to the source electrode of said sixth transistor; connection of the drain electrodes of said seventh and ninth transistors to the input terminal of said inverting amplifier; and an interconnection between the drain electrodes of said eighth and tenth transistors, which interconnection is connected to the gate electrodes of said seventh, eighth, ninth and tenth transistors.
 8. A multiplier as set forth in claim 1 including:third and fourth field effect transistors of one of said first and second conductivity types and fifth and sixth field effect transistors of the other of said first and second conductivity types, each having source and drain and gate electrodes; means connecting said third, fourth, fifth and sixth transistors in bridge connection including a first interconnection between the drain electrodes of said third and fifth transistors connected to the drain electrode of said first transistor, a second interconnection between the drain electrodes of said fourth and sixth transistors connected to the drain electrode of said second transistor, a third interconnection between the source electrodes of said third and fourth transistors, a fourth interconnection between the source electrodes of said fifth and sixth transistors, constant current generator means connected to apply current to said third interconnection, means for applying a direct potential to said fourth interconnection, means for applying gate potentials to said third and fourth transistors including (a) means for adjusting the direct component of one of the gate potentials of said third and fourth transistor vis-a-vis the other and (b) means for applying said multiplier signal differentially between the gate electrodes of said third and fourth transistors, and means for applying gate potentials to said fifth and sixth transistors to bias them into conduction. 